View APW7035CKC-TR_8326722.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. advanced pwm and linear power control features ? ? ? ? ? 2 regulated voltage are provided ? switching power for fixed voltage (1.25v / 2.05v) or adjustable voltage ? linear regulator for fbvddq(2.5v) ? ? ? ? ? simple single-loop control design ? voltage-mode pwm control ? ? ? ? ? excellent output voltage regulation ? pwm output : 1% ? linear output : 3% ? ? ? ? ? fast transient response ? high-bandwidth error amplifier ? full 0% to 100% duty ratio ? ? ? ? ? power-good output voltage monitor ? ? ? ? ? over-voltage and over-current fault monitors ? ? ? ? ? small converter size ? constant frequency operation(200khz) ? reduce external component count applications ? ? ? ? ? motherboard power regulation for computers ? ? ? ? ? low-voltage distributed power supplies ? ? ? ? ? vga card power regulation ? ? ? ? ? termination voltage general description the apw7035 integrates pwm controller and linear controller , as well as the monitoring and protection functions into a single package , which provides two controlled power outputs with over-voltage and over- current protections. the pwm controller regulates the ddr reference voltage (1.25v) or gpu voltage (2.05v) with a synchronous-rectified buck converter. the linear controller regulates power for memory voltage. the precision reference and voltage-mode pwm control provide 1 % static regulation. the linear con- troller drives an external n-channel mosfet to pro- vide adjustable voltage. the apw7035 monitors all the output voltages , and a single power good signal is issued when the pwm voltage is within 10 % of the dac setting and the linear regulator output levels are above their under- voltage thresholds. additional built-in over-voltage pro- tection for the pwm output uses the lower mosfet to prevent output voltages above 115 % of the dac setting. the pwm over-current function monitors the output current by using the voltage drop across the upper mosfet?s r ds(on) , eliminating the need for a current sensing resistor. the apw7035a/b/c/d support a ttl 3-input digital to analog converter that adjusts the synchronous- rectified buck converter output from 1.00v to 3.20v , referenc to table1.
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 2 pin description ordering information block diagram apw7035-12/19 pgood lgate ocset pgnd ugate phase drive vcc ss vsen1 vaux fb comp 1 11 10 12 9 13 16 8 14 15 7 6 17 18 19 20 5 4 3 2 nc nc nc sd vsen2 nc gnd vid0 lgate ocset pgnd ugate phase drive vcc ss vsen1 vaux fb comp 1 11 10 12 9 13 16 8 14 15 7 6 17 18 19 20 5 4 3 2 nc nc vid1 sd vsen2 vid2 gnd apw7035a/b/c/d apw7035 voltage code 12 : 1.25v 20 : 2.05v a : 1.00v~1.35v b : 1.40v~1.75v c : 1.80v~2.40v d : 2.50v~3.20v package code k : sop temp. range c : 0 to 70 c handling code tu : tube tr : tape & reel handling code temp. range package code voltage code pgood power-on reset (por) vcc 200ma 1.10 + - gate control + - pwm comp1 synch drive ov ugate phase v cc lgate pgnd comp fb ocset vsen1 error amp1 pwm1 vcc inhibit oc1 vaux drive + - + - + - + - 0.90 1.15 vaux gnd vsen2 + - 0.75 + - 1.5v + - dac + - soft start & fault logic ss oscillator inhibit sd v cc 28ma 4.5v dac + - vid0 vid1 vid2 v dac
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 3 absolute maximum ratings symbol parameter rating unit v cc supply voltage 15 v v i , v o input , output or i/o voltage gnd -0.3 v to v cc +0.3 v t a operating ambient temperature range 0 to 70 c t j junction temperature range 0 to 125 c t stg storage temperature range -65 to +150 c t s soldering temperature 300 ,10 seconds c electrical characteristics thermal characteristics symbol parameter value unit r ja thermal resistance in free air soic soic (with 3in 2 of copper) 75 65 c/w (recommended operating conditions , unless otherwise noted) refer to block and simplified power system diagrams , and typical application schematic. apw7035 symbol parameter test conditions min. typ. max. unit v cc supply current i cc nominal supply current ugate, lgate, drive open 9ma power-on reset rising vcc threshold vocset=4.5v 10.7 v falling vcc threshold vocset=4.5v 8.2 v rising vaux threshold vocset=4.5v 2.5 v vaux threshold hysteresis vocset=4.5v 0.5 v rising v ocset threshold 1.26 v oscillator f ocs free running frequency rt= open 185 200 215 khz ? v osc ramp amplitude rt= open 1.9 v p-p
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 4 electrical characteristics cont. apw7035 symbol parameter test conditions min. typ. max. unit dac and bandgap reference v dac dacout voltage accuracy -1.0 +1.0 % v bg bandgap reference voltage 1.265 v bandgap reference tolerance -2.5 +2.5 % linear regulators regulation 3 % output drive current vaux-v drive >0.6v 20 40 ma synchronous pwm controller error amplifier dc gain 88 db gbwp gain-bandwidth product 15 mhz sr slew rate comp=10pf 6 v/ s pwm controller gate driver i ugate ugate source v cc =12v, v ugate =6v 1 a r ugate ugate sink v ugate1-phase =1v 3.5 ? i lgate lgate source v cc =12v, v lgate =1v 1 a r lgate lgate sink v lgate = 1v 3 ? protection vsen1 over-voltage vsen1 rising 115 120 % protection i ocset ocset current source v ocset = 4.5v dc 170 200 230 a i ss soft start current 28 a power good vsen1 upper threshold vsen1 rising 109 % vsen1 under voltage vsen1 rising 93 % vsen1 hysteresis upper /lower threshold 2 % v pgood pgood voltage low i pgood = -4ma 0.8 v functional pin description (recommended operating conditions , unless otherwise noted) refer to block and simplified power system diagrams , and typical application schematic. vcc (pin 1) provide a 12v bias supply for the ic to this pin. this pin also provides the gate bias charge for all the mosfets controlled by the ic. the voltage at this pin is monitored for power-on reset (por) purposes. drive (pin 2) connect this pin to the gate of an external mosfet. this pin provides the drive for the fbvddq regulator?s pass transistor.
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 5 functional pin description cont. nc (pin 3, pin 4 and pin 5) no connect. (apw7035-12,19) pgood (pin 5) pgood is an open drain output used to indicate the status of the output voltages. this pin is pulled low when the synchronous regulator output is not within 10% of the dac reference voltage or linear regula- tor outputs are below under-voltage thresholds. (apw7035-a,b,c,d) vid2 , vid1 , vid0 (pin 3,4 and 5) vid0-2 are the ttl-compatible input pins to the 3-bit dac. the logic states of these three pins program the internal voltage reference (dac). the level of dac sets the microprocessor core converter output volt- age , as well as the corresponding pgood and ovp thresholds. (apw7035-a,b,c,d) sd (pin 6) the pin shuts down all the outputs. a tll-compatible , logic lebel high signal applied at this pin immedi- ately discharges the soft-start capacitor , disbling all the output. vsen2 (pin 7) connect this pin to a resistor divider to set the linear regulator (fbvddq) output voltage. ss (pin 8) connect a capacitor from this pin to ground. this capacitor , along with an internal 28 a current source , sets the soft-start interval of the converter. nc (pin 9 and pin12) no connection. vaux (pin 10) this pin provides boost current for the linear regulator?s output drives in the event bipolar npn transistors (instead of n-channel mosfets) are employed as pass elements. the voltage at this pin is monitored for power-on reset purposes. gnd (pin 11) signal ground for the ic. all voltage levels are mea- sured with respect to this pin. fb and comp (pin 13, and 14) comp and fb are the available external pins of the pwm converter error amplifier. the fb pin is the inverting input of the error amplifier. similarly , the comp pin is the error amplifier output. these pins are used to compensate the voltage-mode control feedback loop of the synchronous pwm converter. vsen1 (pin 15) this pin is connected to the pwm converter?s output voltage. the pgood and ovp comparator circuits use this signal to report output voltage status and for over- voltage protection. ocset (pin 16) connect a resistor from this pin to the drain of the respective upper mosfet. this resistor , an inter- nal 200 a current source , and the upper mosfet?s on-resistance set the converter over-current trip point. an over-current trip cycles the soft-start function. the voltage at this pin is monitored for power-on reset (por) purposes and pulling this pin low with an open drain device will shutdown the ic. pgnd (pin 17) this is the power ground connection. tie the syn- chronous pwm converter?s lower mosfet source to this pin. lgate (pin 18) connect lgate to the pwm converter?s lower mosfet gate. this pin provides the gate drive for the lower mosfet.
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 6 simplified power system diagram phase (pin 19) connect the phase pin to the pwm converter?s up- per mosfet source. this pin represents the gate drive return current path and is used to monitor the voltage drop across the upper mosfet for over-cur- rent protection. functional pin description cont. ugate (pin 20) connect ugate pin to the pwm converter?s upper mosfet gate. this pin provides the gate drive for the upper mosfet. table1 output voltage program vid2 vid1 vid0 apw7035-a vid2 vid1 vid0 apw7035-b 0 0 0 1.35v 0 0 0 1.75v 0 0 1 1.30v 0 0 1 1.70v 0 1 0 1.25v 0 1 0 1.65v 0 1 1 1.20v 0 1 1 1.60v 1 0 0 1.15v 1 0 0 1.55v 1 0 1 1.10v 1 0 1 1.50v 1 1 0 1.05v 1 1 0 1.45v 1 1 1 1.00v 1 1 1 1.40v vid2 vid1 vid0 apw7035-c vid2 vid1 vid0 apw7035-d 0 0 0 2.40v 0 0 0 3.20v 0 0 1 2.30v 0 0 1 3.10v 0 1 0 2.20v 0 1 0 3.00v 0 1 1 2.10v 0 1 1 2.90v 1 0 0 2.00v 1 0 0 2.80v 1 0 1 1.90v 1 0 1 2.70v 1 1 0 1.80v 1 1 0 2.60v 11101112.50v linear controller pwm1 controller apw7035 v out1 q2 3.3 v in q1 v out2 q3 5.0v in
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 7 typical application circuit ss comp 8 7 2 10 6 13 15 14 19 18 17 20 5 16 vens1 drive vaux sd vcc fb vens1 pgnd lgate phase ugate pgood ocset gnd 11 1 c2 220pf r4 1.2k c3 330uf c4 10uf c6 330uf r7 64 c5 330uf l1 l2 q2a apm7313 q2b apm7313 r5 5.1 r6 5.1 r9 3k r8 100 c7 10pf r10 150k c8 2700pf c9 0.1uf r3 100 c11 330uf q1 apm3055l c10 330uf c1 1uf r1 10 12v 3.3v 2.5v 2.05v 5.0v apw7035-12 r2 66.7
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 8 package information so ? 300mil ( reference jedec registration ms-013) millimeters variations inches variations dim min. max. variations min. max. dim min. max. variations min. max. a2.35 2.65 so-20 12.60 13.0 a 0.093 0.1043 so-20 0.496 0.512 a1 0.10 0.30 so-24 15.20 15.60 a1 0.004 0.0120 so-24 0.599 0.614 b 0.33 0.51 so-28 17.70 18.11 b 0.013 0.020 so-28 0.697 0.713 c 0.23 0.32 c 0.0091 0.0125 d see variations d see variations e 7.40 7.60 e 0.2914 0.299 2 e 1.27bsc e 0.050bsc h 10 10.65 h 0.394 0.419 h 0.25 0.75 h 0.010 0.029 l 0.40 1.27 l 0.016 0.050 10 8 10 8 12 3 e h d l gauge plane 1 e b a1 a c h*45
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 9 classification reflow profiles package reflow conditions refolw condition (ir/ convection or vpr reflow) physical specifications terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb) lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. packaging 1000 devices per reel convection or ir/ convection vpr average ramp-up rate(183 c to peak) 3 c/second max. 10 c /second max. preheat temperature 125 25 c) 120 seconds max. temperature maintained above 183 c 60 ~ 150 seconds time within 5 c of actual peak temperature 10 ~ 20 seconds 60 seconds peak temperature range 220 +5/-0 c or 235 +5/-0 c 215~ 219 c or 235 +5/-0 c ramp-down rate 6 c /second max. 10 c /second max. time 25 c to peak temperature 6 minutes max. pkg. thickness 2.5mm and all bags pkg. thickness < 2.5mm and pkg. volume 350 mm3 pkg. thickness < 2.5mm and pkg. volume < 350mm3 convection 220 +5/-0 c convection 235 +5/-0 c vpr 215-219 c vpr 235 +5/-0 c ir/convection 220 +5/-0 c ir/convection 235 +5/-0 c reference jedec standard j-std-020a april 1999 pre-heat temperature 183 c peak temperature time temperature
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 10 tape & reel dimensions reliability test program test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms , i tr > 100ma t ao e w po p ko bo d1 d f p1 a j b t2 t1 c application a b c j t1 t2 w p e sop-20 330 1 62 1.5 12.75 0.15 2 + 0.6 24.4 +0.2 2 0.2 24 + 0.3 - 0.1 12 0.1 1.75 0.1 application f d d1 po p1 ao bo ko t sop-20 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 8.2 0.1 13 0.1 2.5 0.1 0.35 0.013 (mm)
copyright ? anpec electronics corp. rev. a.4 - jul., 2001 apw7035 www.anpec.com.tw 11 cover tape dimensions customer service anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 carrier width 24 cover tape width 21.3 (mm)

▲Up To Search▲

Price & Availability of APW7035CKC-TR

	To Download APW7035CKC-TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .